Improving Cache Hit Rate Using The Control Flow Graph

Abstract

This paper provides a technique for designing a cache control unit that speeds up program execution time. This feature is highly required for modern computers to enhance system performance and efficiency. The technique focuses on solving the problem of cache misses by utilizing the control flow graph of the program behavior during its loading from the main memory and executing from the cache by the processor.The proposed cache control unit performs its task in two stages that work in parallel. These stages are implemented by the following circuits: 1- Loader circuit that loads program blocks from main memory into cache lines. 2- Replacement circuit that manages the cache lines by placing the coming program blocks into the proper cache lines and performing the replacement without misses. This solution required that a program has to be logically partitioned according to its control flow graph into basic blocks with one exit point. This results in variable-sized program blocks to be loaded into the cache. There by in the cache there exists a block with its two successors blocks. The selection of next block to be executed from these two successors depends on the condition of the exit point of the parent block (taken or not taken branch). Thus always the next block to be executed is available in the cache. The design of the loader circuit and the replacement circuit are given in details and their functionalities are simulated. Program partitioning and the relations between program blocks are assumed to be collected from other job in a form of profile data. This data is used by the proposed circuit to control its operations and synchronizing its functions