| dc.description.abstract | A large number of adders have been proposed, but adding fast
adder using low area and power is still challenging. In 2001 a
new 32-bit asynchronous adder has been introduced (32-bit
ESTC adder)[1], which used the estimation theory to improve
the speed of addition time. This paper presents a design and
implementation of the necessary control circuit for 32-bit
ESTC adder and compares it's performance and area with
other previous adder designs. It has been seen through analysis
of the design and operation with previous work that the
Estimated Carry Adder provides a compromise between high
speed, high area cost adders (carry lookahead adder) and slow,
low area adders (carry ripple adder). Comparison with wellknown
conventional adders demonstrates that 32-bit ESTC
adder dramatically achieve speeds and/or area advantages over
previously adder circuits. | en_US |
